A silicon carbide semiconductor device having a J-FET (i.e., a junction field effect transistor) formed therein by the use of a silicon carbide semiconductor substrate has been proposed. The device is disclosed, for example, in Japanese Patent Application Publication No. 2003-068761-A. The sectional construction of this silicon carbide semiconductor device is shown in FIG. 18.
In this silicon carbide semiconductor device, a substrate J6 is used in which an N− type drift layer J2, a P+ type first gate layer J3, and an N+ type source layer J5 are formed in sequence on the surface of an N+ type substrate J1. The silicon carbide semiconductor device has a construction in which a trench J7 passing through the N+ type source layer J5 and the P+ type first gate layer J3 is formed in the substrate J6 and in which an N− type channel layer J8 and a P+ type second gate layer J9 are arranged in the trench J7.
With this structure, a normally-off type J-FET is constructed in which the N− type channel layer J8 is sandwiched by the P+ type first and second gate layers J3 and J9, whereby the N− type channel layer J7 side is completely depleted by a depletion layer extending from the P+ type first and second gate layers J3 and J9 even in a state where voltage is not applied across the P+ type first and second gate layers J3 and J9.
On the other hand, various researches on a semiconductor device technology have been conducted so as to reduce the size of a cell. In order to reduce the size of a cell, also in the silicon carbide semiconductor device, the layout construction of a wiring structure becomes important.
For example, a vertical power MOSFET having a sectional construction shown in FIG. 19 has been known. The MOSFET is disclosed, for example, in Japanese Patent Application Publication No. 2003-188380. In this vertical power MOSFET, a trench J13 is formed in such a way as to pass through a P type base layer J11 and a source region J12, and a gate electrode J15 is formed in the trench J13 via an oxide film J14. The vertical power MOSFET has a construction in which a gate wiring electrically connected to the gate electrode J15 and a source wiring J16 electrically connected to both of the source region J12 and the P type base layer J11 are electrically separated from each other.
In this construction, the N+ type source layer J12 and the P type base layer J11 provide common electrodes, so that the layout of the source wiring is not so difficult and the size of a cell can be easily reduced.
However, in the silicon carbide semiconductor device provided with the J-FET of the structure described above, both of the source wiring electrically connected to the N+ type source layer and a gate wiring electrically connected to the P+ type first gate layer and the P+ type second gate layer are disposed on the main surface side of the substrate. For this reason, the layout of the source wiring is limited by the gate wiring to increase difficulty in layout. Depending on the layout of the source wiring and the gate wiring, this leads to enlarging the size of a cell, which is not preferable.